1. Field of the Invention
This invention relates to a manufacturing method for a semiconductor device, and more particularly, to a manufacturing method for a semiconductor device, including forming a fine pattern of a size smaller than a resolution limit of lithography using side wall spacers as a mask.
2. Description of the Related Art
A photolithography technique in a conventional semiconductor technology generally involves etching a base silicon substrate and a silicon oxide film using as a mask a photoresist pattern obtained by exposure and development through a photomask. However, as the pattern becomes finer, a type of light source used in the exposure has been changed, with the result that an etching resistance of a photoresist suited to the light source has been lowered. Therefore, the following technique is frequently used for pattern formation. That is, the pattern is once transferred by etching to a base film (for example, silicon nitride film) having a thickness that is relatively thin but thick enough to enable the photoresist to endure, using as a mask the photoresist pattern obtained through the photomask. Then, an original layer to be processed (for example, silicon oxide film), which is a base film of the silicon nitride film, is etched using the silicon nitride film as a mask, to thereby form the pattern. A silicon nitride film patterned in this manner is called a hard mask.
In recent years, demands for miniaturization and higher density of a semiconductor memory or the like have surpassed a development speed of a lithography technique concerning, for example, an exposure apparatus or a photoresist. As a result, a method of forming a pattern of a size smaller than a resolution limit of lithography has attracted attention. As an example of such a method, Patent Document 1 (U.S. Pat. No. 6,063,688) discloses a technology of etching a layer under side wall spacers using the side wall spacers as a hard mask, to thereby form a fine pattern of a size smaller than a resolution limit of lithography.
In the method of forming a pattern using the side wall spacers as a hard mask, there are some points to be considered with regard to the side wall spacers. For example, (1) only a pattern having a fixed width that is determined by a film thickness of the side wall spacers may be formed, and thus the side wall spacers may not serve to form a pattern of an arbitrary size. (2) Both in a case where the side wall spacers are formed on outer side walls in an island-like pattern and in a case where the side wall spacers are formed on inner walls of an opening portion formed in an insulating layer, the side wall spacers are formed inevitably in a “loop-like” shape. When a line-and-space pattern is formed, end portions of different lines or end portions of different spaces are connected to each other, which requires to isolate a line pattern or a space pattern. (3) There is no mask pattern in a region in which the hard mask of the side wall spacers is not formed. Therefore, in a case where a space pattern or a hole pattern of a size smaller than a resolution limit of lithography is formed using the side wall spacers as a hard mask, it is necessary to prepare a large pattern that covers an entire surface of a region other than a region in which the above-mentioned fine patterns are formed.
In the technology disclosed in Patent Document 1, an entire surface of a substrate other than a channel region in which the hard mask of the fine side wall spacers is formed is covered with a photoresist. The substrate is etched using the photoresist and the hard mask of the side wall spacers as masks. In this manner, a fine trench pattern is formed only in the channel region on the substrate.
According to the technology described above, the region other than the channel region is covered with the resist, and hence an unnecessary trench is prevented from being formed. Further, the end portions of different lines or the end portions of different spaces are not connected to each other in the line-and-space pattern of the channel region, to thereby achieve isolating the space pattern.
Meanwhile, Patent Document 2 (Japanese Unexamined Patent Application Publication (JP-A) No. 2008-27978) discloses a method of forming a fine pattern of a size smaller than a resolution limit of lithography and, at the same time, forming a pattern of an arbitrary size using side wall spacers as a hard mask.
According to the method disclosed in Patent Document 2, a first core pattern for forming a hard mask of side wall spacers and a second core pattern for forming a pattern of an arbitrary size are formed on a semiconductor substrate in the same photolithography step. Side wall spacers are formed on both side walls of the first core pattern and side walls of the second core pattern. After that, the first core pattern is selectively removed while the second core pattern is left. The second core pattern is also used as a hard mask, to thereby form a hard mask of an arbitrary size.    Patent Document 1: U.S. Pat. No. 6,063,688    Patent Document 2: Japanese Unexamined Patent Application Publication (JP-A) No. 2008-27978